Fault Tolerant and Congestion-Aware Routing Algorithm in a Partially Connected 3D Network on Chip

Document Type : Technical Note

Authors

1 Department of Electrical and Computer Engineering, Science and Research Branch, Islamic Azad University, Tehran, Iran

2 Vehicle Engineering Research Group, Research Center of Technology and Engineering, Standard Research Institute, Karaj, Iran

10.22034/asas.2024.448026.1054

Abstract

Abstract— Network-on-Chips (NoCs) have been accepted as a viable communication platform in many-core systems. However, they possess high network latency and consume large power. In this paper, we introduce a minimal routing algorithm in partially connected 3D Network-on-Chip, in which a fixed place of TSVs is designed to reduce TSV implementation cost which can be provided as a standard in the automotive electronics industry. This routing algorithm employs network congestion and fault information to find the minimum path while avoiding traversing the faulty paths. The proposed algorithm consists of in-layer routing and interlayer routing. The intra-layer routing algorithm employs an information propagation network to propagate control information between nodes located in the same layer. It uses a parameter called index to select the optimum path between nodes in the same layer. The index value is updated periodically based on a faulty link or a faulty node and published across networks. The interlayer routing algorithm is performed based on the minimum path to the elevator routers. The proposed algorithm reduces the average packet latency and increases the network throughput. The simulation results indicate that our routing algorithm improves network latency by 15.3% compared to two other routing algorithms.

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Advances in the Standards & Applied Sciences
Volume 2, Issue 2
March 2024
Pages 58-64

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