Document Type : Original Article
Department of Electrical and Computer Engineering, Science and Research Branch, Islamic Azad University, Tehran, Iran
School of Electrical Engineering Iran University of Science and Technology, Tehran, Iran
Abstract— Network-on-Chips (NoCs) as a standard interconnection impose high latency and excessive power consumption in many-core systems. Emerging data-intensive applications possess a high volume of data movement across the network which deteriorates the network congestion condition. These applications have an intrinsic feature, namely error tolerance, which presents a new communication paradigm. We employ a differential-based approximate method for packet transmission to reduce the packet size on the network. General NoC architectures have a large enough flit channel so that the packet header includes many free bits. As we reduce the packet size by transmitting the difference data on the network, we can accommodate the additional parts of the header to store the difference data that must be transmitted. This approach in data storage and transmission optimizes the packet size, which reduces the network congestion by using the idle space of head flit and employing approximate-based data transmission. We apply this method in 3D NoC due to its low latency architecture. Therefore, we could alleviate 3D NoC thermal challenges. The simulation results show that our approximate-based NoC architecture decreases the latency and dynamic power consumption by 37% and 42% in comparison to traditional 3D NoC, respectively.